82801CA Datasheet, PDF (415/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.1.4
13.1.5
13.1.6
PCISTS—PCI Device Status Register (Audio—D31:F5)
Offset:
Default Value
Lockable:
06–07h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16 bits
Core
PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
Description
15 Detected Parity Error (DPE). Not implemented. Hardwired to 0.
14 Signaled System Error (SSE). Not implemented. Hardwired to 0.
Master Abort Status (MAS)—R/WC.
13 _{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Bus Master AC ’97 2.2 interface function, as a master, generates a master abort.
12 Reserved. Will always read as 0.
11 Signaled Target Abort (STA). Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS)—RO. This 2-bit field reflects the ICH3's DEVSEL# timing
10:9 ^{when performing a positive decode.}
01b = Medium timing.
8
Data Parity Error Detected (DPED). Not implemented. Hardwired to 0.
7
Fast Back to Back (FB2B). Hardwired to 1. This bit indicates that the ICH3 as a target is capable of
fast back-to-back transactions.
6
User Definable Features (UDF). Not implemented. Hardwired to 0.
5
66 MHz Capable (66MHZ_CAP). Hardwired to 0.
4:0 Reserved. Read as 0s.
RID—Revision Identification Register (Audio—D31:F5)
Offset:
Default Value:
Lockable:
08h
See Note
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
Bit
7:0 Revision Identification Value—RO.
Description
NOTE: Refer to the Specification Update for the Revision ID.
PI—Programming Interface Register (Audio—D31:F5)
Offset:
09h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
7:0 Programming Interface Value—RO.
Description
Intel^® 82801CA ICH3-S Datasheet
415