82801CA Datasheet, PDF (262/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.4
PD_STS—Primary Device Status Register
(HUB-PCI—D30:F0)
Offset Address: 06–07h
Default Value: 0080h
Attribute:
Size:
R/WC
16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
Bit
Description
Detected Parity Error (DPE)—R/WC.
15 ^{0 = Software clears this bit by writing a 1 to the bit location.}
1 = Indicates that the ICH3 detected a parity error on the hub interface. This bit gets set even if the
Parity Error Response bit (offset 04, bit 6) is not set.
Signaled System Error (SSE)—R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
14 ^{1 = An address, or command parity error, or special cycles data parity error has been detected on}
the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set
because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH3
will generate an NMI (or SMI# if NMI routed to SMI#).
Received Master Abort (RMA)—R/WC.
13 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = ICH3 received a master abort from the hub interface device.
Received Target Abort (RTA)—R/WC.
12 ^{0 = Software clears this bit by writing a 1 to the bit location.}
1 = ICH3 received a target abort from the hub interface device. The TCO logic can cause an SMI#,
NMI, or interrupt based on this bit getting set.
Signaled Target Abort (STA)—R/WC.
11 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = ICH3 signals a target abort condition on the hub interface.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter.
Master Data Parity Error Detected (MDPD)—R/WC. Since this register applies to the hub
interface, the ICH3 must interpret this bit differently than it is in the PCI spec.
8 _{0 = Software clears this bit by writing a 1 to the bit location.}
1 = ICH3 detects a parity error on the hub interface and the Parity Error Response bit in the
Command Register (offset 04h, bit 6) is set.
7 Fast Back to Back (FB2B)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
4:0 Reserved.
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Intel^® 82801CA ICH3-S Datasheet