82801CA Datasheet, PDF (402/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.1.9
SVID—Subsystem Vendor ID Register (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem Vendor ID—RO. The SVID register, in combination with the Subsystem ID (SID)
15:0
register, enables the operating system (OS) to distinguish subsystems from each other. The value
returned by reads to this register is the same as that which was written by BIOS into the IDE_SVID
register.
12.1.10
SID—Subsystem ID Register (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem ID—R/Write-Once. The SID register, in combination with the SVID register, enables the
15:0 operating system (OS) to distinguish subsystems from each other. The value returned by reads to
this register is the same as that which was written by BIOS into the IDE_SID register.
12.1.11
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value: 00h
Attributes:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN)—R/W. This data is not used by the ICH3. It is to communicate to software
the interrupt line that the interrupt pin is connected to PIRQB#.
12.1.12
INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value: 02h
Attributes:
Size:
RO
8 bits
Bit
Description
Interrupt Pin (INT_PN)—RO.
7:0
02h = Indicates that the ICH3 SMBus Controller will drive PIRQB# as its interrupt line.
402
Intel^® 82801CA ICH3-S Datasheet