82801CA Datasheet, PDF (366/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.1
10.1.2
VID—Vendor ID Register (IDE—D31:F1)
Offset Address: 00–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
Bit
Description
15:0 Vendor Identification Value—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h.
DID—Device ID Register (IDE—D31:F1)
Offset Address: 02–03h
Default Value: 248Bh
Attribute:
Size:
RO
16 bits
10.1.3
Bit
Device Identification Value—RO.
15:0
DID = 248Bh
Description
CMD—Command Register (IDE—D31:F1)
Address Offset: 04h–05h
Default Value: 00h
Attribute:
Size:
RO, R/W
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—RO. Hardwired to 0.
Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—RO. Hardwired to 0.
VGA Palette Snoop (VPS)—RO. Hardwired to 0.
Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W. Controls the ICH3’s ability to act as a PCI master for IDE Bus
Master transfers.
0 = Disable
1 = Enable.
Memory Space Enable (MSE)—R/W.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The EXBAR register (Offset 24h) must
be programmed before this bit is set.
NOTE: BIOS should set this bit to a 1.
I/O Space Enable (IOE)—R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as
the Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
disable the Primary or Secondary I/O spaces.
2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see
Section 11.1.14) will be masked (the interrupt will not be asserted).
If an interrupt occurs while the masking is in place and the interrupt is still active when the
masking ends, the interrupt will be allowed to be asserted.
366
Intel^® 82801CA ICH3-S Datasheet