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82801CA Datasheet, PDF (233/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S) | |||
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Register and Memory Mapping
6.4
Memory Map
Table 6-5 shows (from the processor perspective) the memory ranges that the ICH3 will decode.
Cycles that arrive from the Hub Interface that are not directed to any of the internal memory targets
that decode directly from Hub Interface will be driven out on PCI. The ICH3 may then claim the
cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is
enabled, the cycle can be forwarded to LPC.
PCI cycles generated by an external PCI master will be positively decoded unless it falls in the
PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If the
cycle is not in the I/O APIC or LPC ranges, it will be forwarded up the hub interface to the Host
Controller. PCI masters can not access the memory ranges for functions that decode directly from
Hub Interface
Table 6-5. Memory Decode Ranges from Processor Perspective
Memory Range
Target
Dependency/Comments
0000 0000â000D FFFFh
0010 0000âTOM
(Top of Memory)
000E 0000â000F FFFFh
FEC0 0000âFEC0 0100h
FFC0 0000âFFC7 FFFFh
FF80 0000âFF87 FFFFh
FFC8 0000âFFCF FFFFh
FF88 0000âFF8F FFFFh
FFD0 0000âFFD7 FFFFh
FF90 0000âFF97 FFFFh
FFD8 0000âFFDF FFFFh
FF98 0000âFF9F FFFFh
FFE0 000âFFE7 FFFFh
FFA0 0000âFFA7 FFFFh
FFE8 0000âFFEF FFFFh
FFA8 0000âFFAF FFFFh
FFF0 0000âFFF7 FFFFh
FFB0 0000âFFB7 FFFFh
FFF8 0000âFFFF FFFFh
FFB8 0000âFFBF FFFFh
FF70 0000âFF7F FFFFh
FF30 0000âFF3F FFFFh
FF60 0000âFF6F FFFFh
FF20 0000âFF2F FFFFh
FF50 0000âFF5F FFFFh
FF10 0000âFF1F FFFFh
FF40 0000âFF4F FFFFh
FF00 0000âFF0F FFFFh
Main Memory TOM registers in Host Controller
FWH
I/O APIC inside
ICH3
Bit 7 in FWH Decode Enable Register is set
FWH
Bit 0 in FWH Decode Enable Register
FWH
Bit 1 in FWH Decode Enable Register
FWH
Bit 2 in FWH Decode Enable Register is set
FWH
Bit 3 in FWH Decode Enable Register is set
FWH
Bit 4 in FWH Decode Enable Register is set
FWH
Bit 5 in FWH Decode Enable Register is set
FWH
FWH
FWH
Bit 6 in FWH Decode Enable Register is set.
Always enabled.
The top two 64K-byte blocks of this range can be
swapped, as described in Section 6.4.1.
Bit 3 in FWH Decode Enable 2 Register is set
FWH
Bit 2 in FWH Decode Enable 2 Register is set
FWH
Bit 1 in FWH Decode Enable 2 Register is set
FWH
Bit 0 in FWH Decode Enable 2 Register is set
Intel® 82801CA ICH3-S Datasheet
233
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