82801CA Datasheet, PDF (136/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-36 shows the transitions rules among the various states. Note that transitions among the
various states may appear to temporarily transition through intermediate states. For example, in
going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate
transitions and states are not listed in the table.
Table 5-36. State Transition Rules for Intel^® ICH3
Present
State
G0/S0/C0
G0/S0/C1
G0/S0/C2
G1/S1,
G1/S3 or
G1/S4
G2/S5
Transition Trigger
• Processor halt instruction
• Level 2 Read
•
• SLP_EN bit set
• Power Button Override
• Mechanical Off/Power Failure
• Any Enabled Break Event
• STPCLK# goes active
• Power Button Override
• Power Failure
• Any Enabled Break Event
• STPCLK# goes inactive and previously
in C1
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Failure
G3
• Power Returns
Next State
• G0/S0/C1
• G0/S0/C2
• G1/Sx or G2/S5state
• G2/S5
• G3
• G0/S0/C0
• G0/S0/C2
• G2/S5
• G3
• G0/S0/C0
• G0/S0/C1
• G2/S5
• G3
• G0/S0/C0
• G2/S5
• G3
• G0/S0/C0
• G3
• Optional to go to S0/C0 (reboot) or G2/S5
(stay off until power button pressed or other
wake event).
(See Note 1)
NOTES:
1. Some wake events can be preserved through power failure.
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Intel^® 82801CA ICH3-S Datasheet