82801CA Datasheet, PDF (492/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Testability
Table 18-6. XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks While PWROK Active)
Pin Name
SDD8
SDD6
SDD5
SDD7
SDD10
SDD11
SDD3
SDD9
SDD12
SDD15
SDD4
SDIOW#
SDD2
SDD0
SDDREQ
SDD14
SDD13
SDD1
SIORDY
SDIOR#
SDDACK#
SDA1
SDA2
SDA0
SDCS3#
SDCS1#
HI7
HI11
HI6
HI5
HI9
HI4
HI_STBS
HI10
HI3
HI8
HI1
HI2
Ball #
Notes
W13
AA13
Top of XOR Chain
2nd signal in XOR
Y14
W15
Y15
AC16
AB16
Y16
AB17
AC18
W16
AA18
AC17
Y17
AB18
Y18
AA17
W17
AB19
AC19
Y19
AA19
AB20
AC20
AC22
AC21
T23
R19
R20
R22
P19
P21
N22
N19
N20
M19
M21
M23
Pin Name
GPIO42
GPIO8
PME#
GPIO25
PCIRST#
GPIO13
GPIO28
GPIO12
SLP_S5#
GPIO27
SMLINK1
PWRBTN#
GPIO[24]
SMLINK0
SUSCLK
SUS_STAT#
SMBCLK
SLP_S3#
SMBDATA
SMBALERT#/
GPIO11
OC4#
OC3#
OC2#
OC1#
OC5#
AC_SDIN0
AC_RST#
USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
Ball #
D23
W2
W1
W3
Y1
Y2
Y3
Y4
AA2
W4
AB2
AB1
AC2
AC3
AA4
AB4
AC4
AA5
AB5
AC5
A12
B12
C12
D12
A11
B11
D11
D19
D18
A19
A18
E17
E16
B17
B16
D15
D14
A15
Notes
492
Intel^® 82801CA ICH3-S Datasheet