82801CA Datasheet, PDF (345/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.9
GPE1_STS—General Purpose Event 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ch
(ACPI GPE1_BLK)
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI
Note: This register is symmetrical to the General Purpose Event 1 Enable Register. GPIOs that are not
implemented will not have the corresponding bits implemented in this register.
Bit
Description
GPI[n]_STS—R/WC.
0 = Software clears each bit by writing a 1 to the bit position when the corresponding GPIO signal
is not active. (The status bit cannot be cleared while the corresponding signal is still active).
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is low (or high if the corresponding GP_INV bit is set).
15:0
If the corresponding GPI[n]_EN bit is set in the GPE1_EN register, and the GPI[n]_STS bit is
set, then:
- If the system is in an S1_S5 state, the event will also wake the system.
- If the system is in an S0 state (or upon waking back to an S0 state), an SMI# or SCI will be
generated, depending on the GPI_ROUT bits for the corresponding GPI.
9.8.3.10
GPE1_EN—General Purpose Event 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Eh
(ACPI GPE1_BLK + 2)
0000h
No
Resume
Attribute:
Size:
Usage:
R/W
16-bit
ACPI
Note:
This register is symmetrical to the General Purpose Event 1 Status Register. GPIOs that are not
implemented will not have the corresponding bits implemented in this register. All of the bits in
this register will be cleared by RSMRST#. The ICH3 uses the same GPE1_EN register (I/O
address: PMBase+2Eh) to enable/disable both SMI and ACPI SCI general purpose input events.
APCI OS assumes that it owns the entire GPE1_EN register per ACPI spec. Problems arise when
some of the general-purpose inputs are enabled as SMI by BIOS, and some of the general purpose
inputs are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input
signals that are not indicated as SCI general-purpose events at boot, and exit from sleeping states.
BIOS should define a dummy control method which prevents the ACPI OS from clearing the SMI
GPE1_EN bits.
Bit
Description
GPI[n]_EN—R/W.
15:0 _{0 = Disable.}
1 = Enable the corresponding GPI[n]_STS bit being set to cause an SMI#, SCI, and/or wake event.
Intel^® 82801CA ICH3-S Datasheet
345