82801CA Datasheet, PDF (445/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Modem Controller Registers (D31:F6)
Bit
Description
PCM In Interrupt (PIINT)—RO. This bit indicates that one of the PCM in channel interrupts
occurred.
5
0 = When the specific interrupt is cleared, this bit will be cleared.
1 = Interrupt occurred.
4:3 Reserved.
Modem Out Interrupt (MOINT)—RO. This bit indicates that one of the modem out channel
interrupts occurred.
2
0 = When the specific interrupt is cleared, this bit will be cleared.
1 = Interrupt occurred.
Modem In Interrupt (MIINT)—RO. This bit indicates that one of the modem in channel interrupts
occurred.
1
0 = When the specific interrupt is cleared, this bit will be cleared.
1 = Interrupt occurred.
GPI Status Change Interrupt (GSCI)—RWC. This bit reflects the state of bit 0 in slot 12, and is set
whenever bit 0 of slot 12 is set. This happens when the value of any of the GPIOs currently defined
0 ^{as inputs changes.}
0 = Cleared by writing a 1 to this bit position.
1 = Input changed.
Note: On reads from a codec, the controller will give the codec a maximum of 4 frames to respond, after
which if no response is received, it will return a dummy read completion to the processor (with all
If’s on the data) and also set the read completion status bit in the global status register.
14.2.10
CAS—Codec Access Semaphore Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 44h
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
7:1 Reserved.
Codec Access Semaphore (CAS) —R/W (special). This bit is read by software to check whether a
codec access is currently in progress.
0 _{0 = No access in progress.}
1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform
an I/O access. Once the access is completed, hardware automatically clears this bit.
Intel^® 82801CA ICH3-S Datasheet
445