82801CA Datasheet, PDF (68/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Figure 5-3. NMI# Generation Logic
IOCHK From SERIRQ Logic
NMI_SC [IOCHK_NMI_EN]
AND
NMI_SC
[IO C H K _ N M I_ S T S ]
N M I_S C
[P C I_S E R R _ E N ]
AND
NMI_SC
[SERR#_NMI_STS]
D30:F0 SECSTS
[S S E ]
OR
D30:F0 PDSTS
[SSE]
TCO1_STS
[H U B N M I_S T S ]
OR
TCO1_CNT
[NMI_NOW ]
OR
Hub Interface Parity Error
Detected
D30:F0 CMD
[Parity Error Response]
AND
D30:F0 PD_STS
[DPD]
PCI Parity Error detected
during AC'97, IDE or USB
Master Cycle
D30:F0 BRIDGE_CNT [Parity
Error Response Enable]
AND
OR
D30:F0 SECSTS
[D P D ]
AND
To NMI#
O u tp u t
and
Gating
Logic
PCI Parity Error detected during
LPC or Legacy DMA Master
Cycle
D31:F0 PCICMD
[PER]
AND
N M I_E N
[N M I_E N ]
D31:F0 PCISTA
[DPED]
ich2 nmi
5.1.5 Parity Error Detection
The ICH3 can detect and report different parity errors in the system. The ICH3 can be programmed
to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The
conceptual logic diagram in Figure 5-3 details all the parity errors that the ICH3 can detect, along
with their respective enable bits, status bits, and the results.
Note: If NMIs are enabled, and parity error checking on PCI is also enabled, then parity errors will cause
an NMI. Some operating systems will not attempt to recover from this NMI, since it considers the
detection of a PCI error to be a catastrophic event.
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Intel^® 82801CA ICH3-S Datasheet