82801CA Datasheet, PDF (102/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.5.14
5.6
5.6.1
5.6.2
SYNC field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended
through a SYNC field during the DMA transfer, the peripheral must obey the following rule when
initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is indicated
through the SYNC field. This is needed to allow the 8237, which typically runs off a much slower
internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next
agent.
Under default operation, the host will only perform 8-bit transfers on 8-bit channels and 16-bit
transfers on 16-bit channels.
The method by which this communication between host and peripheral through system BIOS is
performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are
motherboard devices, no “plug-n-play” registry is required.
The peripheral must not assume that the host will be able to perform transfer sizes that are larger
than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller
than what it may currently have buffered.
To that end, it is recommended that future devices which may appear on the LPC bus, which
require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and
not rely on the 8237.
Intel^® 8254 Timers (D31:F0)
The ICH3 contains three counters which have fixed uses. All registers and functions associated
with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is typically
programmed for Mode 3 operation. The counter produces a square wave with a period equal to the
product of the counter period (838 ns) and the initial count value. The counter loads the initial
count value one counter period after software writes the count value to the counter I/O address. The
counter initially asserts IRQ0 and decrements the count value by two each counter period. The
counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and
again decrements the initial count value by two each counter period. The counter then asserts IRQ0
when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately
asserting and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode 2 operation.
The counter negates refresh request for one counter period (838 ns) during each count cycle. The
initial count value is loaded one counter period after being written to the counter I/O address. The
counter initially asserts refresh request, and negates it for 1 counter period when the count value
reaches 1. The counter then asserts refresh request and continues counting from the initial count
value.
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Intel^® 82801CA ICH3-S Datasheet