82801CA Datasheet, PDF (114/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.8.2 Interrupt Mapping
The I/O APIC within the ICH3 supports 24 APIC interrupts. Each interrupt has its own unique
vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of
the Multi-processor specification.
Table 5-17. APIC Interrupt Mapping
IRQ #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Via
SERIRQ
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
N/A
N/A
N/A
N/A
Direct from
pin
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes¹
PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#
PIRQ[E]#
PIRQ[F]#
PIRQ[G]#
PIRQ[H]#
Via PCI
message
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Internal Modules
Cascade from 8259 #1
8254 Counter 0
RTC
Option for SCI, TCO
Option for SCI, TCO
Option for SCI, TCO
FERR# logic
USB 1.1 Controller #1
AC ’97 Audio, Modem, option for SMBus
USB 1.1 Controller #3, Native IDE
USB 1.1 Controller #2
LAN, option for SCI, TCO
Option for SCI, TCO
Option for SCI, TCO
Option for SCI, TCO
Note: IRQ 14 and 15 can only be driven directly from the pins when in legacy IDE mode.
Note: When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15
receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low
internal interrupt sources.
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Intel^® 82801CA ICH3-S Datasheet