82801CA Datasheet, PDF (264/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.9
8.1.10
8.1.11
8.1.12
HEADTYP—Header Type Register (HUB-PCI—D30:F0)
Offset Address: 0Eh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device—RO. This bit is 0 to indicate a single function device.
6:0
Header Type—RO. 8-bit field identifies the header layout of the configuration space, which is a PCI-
to-PCI bridge in this case.
PBUS_NUM—Primary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Primary Bus Number—RO. This field indicates the bus number of the hub interface and is hardwired
to 00h.
SBUS_NUM—Secondary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 19h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Secondary Bus Number—R/W. This field indicates the bus number of PCI.
7:0 _{NOTE: When this number is equal to the primary bus number (i.e., bus #0), the ICH3 will run hub}
interface configuration cycles to this bus number as Type 1 configuration cycles on PCI.
SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)
Offset Address: 1A
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Subordinate Bus Number—R/W. This field specifies the highest PCI bus number below the hub
7:0
interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the
Secondary-to-Subordinate Bus ranges of Device 30, the ICH3 will indicate a master abort back to
the hub interface.
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Intel^® 82801CA ICH3-S Datasheet