82801CA Datasheet, PDF (424/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.2.4
x_SR—Status Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 06h (PISR),
NABMBAR + 16h (POSR),
NABMBAR + 26h (MCSR)
0001h
No
Attribute:
Size:
Power Well:
R/WC, RO
16 bits
Core
Bit
Description
15:5 Reserved.
FIFO Error (FIFOE)—R/WC.
0 = Cleared by writing a 1 to this bit position.
1 = FIFO error occurs.
PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers don't increment, the
4 incoming data is not written into the FIFO, thus is lost.
POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this case should
be the last valid sample.
The ICH3 will set the FIFOE bit if the under-run or overrun occurs when there are more valid buffers
to process.
Buffer Completion Interrupt Status (BCIS)—R/WC.
0 = Cleared by writing a 1 to this bit position.
3
1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt
on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active
until cleared by software.
Last Valid Buffer Completion Interrupt (LVBCI)—R/WC.
0 = Cleared by writing a 1 to this bit position.
1 = Last valid buffer has been processed. It remains active until cleared by software. This bit
indicates the occurrence of the event signified by the last valid buffer being processed. Thus
this is an event status bit that can be cleared by software once this event has been
2
recognized. This event will cause an interrupt if the enable bit in the Control Register is set.
The interrupt is cleared when the software clears this bit.
In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid buffer has
been fetched (not after transmitting it). While in the case of Receives, this bit is set after the
data for the last buffer has been written to memory.
Current Equals Last Valid (CELV)—RO.
0 = Cleared by hardware when controller exists state (i.e., until a new value is written to the LVI
register.)
1
1 = Current Index is equal to the value in the Last Valid Index Register, and the buffer pointed to by
the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is
very similar to bit 2, except this bit reflects the state rather than the event. This bit reflects the
state of the controller, and remains set until the controller exits this state.
DMA Controller Halted (DCH)—RO.
0 1 = Halted. This could happen because of the Start/Stop bit being cleared, or it could happen once
the controller has processed the last valid buffer (in which case it will set bit 1 and halt).
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32-bit read from address offset 04h. Software can also read this register individually by doing a
single 16-bit read to offset 06h.
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Intel^® 82801CA ICH3-S Datasheet