82801CA Datasheet, PDF (148/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Sleep Button
The ACPI specification defines an optional Sleep button. It differs from the power button in that it
only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake
the system, but the Sleep Button cannot.
Although the ICH3 does not include a specific signal designated as a Sleep Button, one of the
GPIO signals can be used to create a “Control Method” Sleep Button. See the ACPI specification
for implementation details.
5.12.9.2 RI#—Ring Indicate
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-45 shows
when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH3
will generate an interrupt based on RI# active, and the interrupt will be set up as a break event.
Table 5-45. Transitions Due to RI# Signal
Present State
S0
S1–S5
Event
RI# Active
RI# Active
RI_EN
X
0
1
Event
Ignored
Ignored
Wake Event
Note: Filtering/Debounce on RI# will not be done in ICH3. This can be in a modem or external.
5.12.9.3
PME#—PCI Power Management Event
The PME# signal comes from a PCI device to request that the system be restarted. The PME#
signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#
signal goes from high to low. No event is caused when it goes from low to high.
In the EHCI controller, there is an internal PME_B0 bit. This is separate from the external PME#
signal and can cause the same effect.
5.12.10
ALT Access Mode
Before entering a low-power state, several registers from powered down parts may need to be
saved. In the majority of cases, this is not an issue, as registers have read and write paths. However,
several of the ISA compatible registers are either read only or write only. To get data out of write-
only registers, and to restore data into read-only registers, the ICH3 implements an ALT access
(alternative access) mode.
If the ALT access mode is entered and exited after reading the registers of the ICH3 timer (8254),
the timer starts counting faster (13.5 ms). The following steps listed below can cause problems:
• BIOS enters ALT access mode for reading the ICH3 timer related registers.
• BIOS exits ALT access mode.
• BIOS continues through the execution of other needed steps and passes control to the OS.
After getting control in step #3, if the OS does not reprogram the system timer again the timer ticks
may be happening faster than expected. For example DOS and its associated software assume that
the system timer is running at 54.6 ms and as a result the timeouts in the software may be
happening faster than expected.
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Intel^® 82801CA ICH3-S Datasheet