82801CA Datasheet, PDF (67/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Figure 5-1. Primary Device Status Register Error Reporting Logic
D30:F0 BRIDGE_CNT
[Parity Error Response Enable]
D30:F0 BRIDGE_CNT
[SERR# Enable]
PCI Address Parity Error
AND
AND
D30:F0 CMD
[SERR_EN]
OR
Delayed Transaction Tim eout
D30:F0 ERR_CMD
[SERR_DTT_EN]
SERR# Pin
D30:F0 BRIDGE_CNT
[SERR# Enable]
D30:F0 ERR_CMD
[SERR_RTA_EN]
Received Target Abort
D30:F0 ERR_STS
[SERR_DTT]
AND
D30:F0 CMD
[SERR_EN]
AND
AND
OR
AND
D30:F0 PD_STS
[SSE]
D30:F0 ERR_STS
[SERR_RTA]
Figure 5-2. Secondary Status Register Error Reporting Logic
D30:F0.04h.8 CMD
[SERR_En]
PCI Delayed Transaction Timeout
D31:F0 D31_ERR_CFG
[SERR_DTT_EN]
AND
LPC Device Signaling an Error
IOCHK# via SERIRQ
OR
TCO1_STS
[H U B E R R _ S T S ]
D31:F0 D31_ERR_CFG
[SERR_RTA_EN]
Received Target Abort
AND
AND
D30:F0 SECSTS
[SSE]
Intel^® 82801CA ICH3-S Datasheet
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