82801CA Datasheet, PDF (503/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-2. Intel^® ICH3 Fixed I/O Registers
Register Name
Channel 0 DMA Base & Current
Address Register
Channel 0 DMA Base & Current
Count Register
Channel 1 DMA Base & Current
Address Register
Channel 1 DMA Base & Current
Count Register
Channel 2 DMA Base & Current
Address Register
Channel 2 DMA Base & Current
Count Register
Channel 3 DMA Base & Current
Address Register
Channel 3 DMA Base & Current
Count Register
Port
00h
01h
02h
03h
04h
05h
06h
07h
Channel 0–3 DMA Command
Register
08h
Channel 0–3 DMA Status Register
Channel 0–3 DMA Write Single
Mask Register
Channel 0–3 DMA Channel Mode
Register
Channel 0–3 DMA Clear Byte
Pointer Register
Channel 0–3 DMA Master Clear
Register
Channel 0–3 DMA Clear Mask
Register
Channel 0–3 DMA Write All Mask
Register
Aliased at 00–0Fh
Master PIC ICW1 Init. Cmd Word 1
Register
Master PIC OCW2 Op Ctrl Word 2
Register
Master PIC OCW3 Op Ctrl Word 3
Register
Master PIC ICW2 Init. Cmd Word 2
Register
Master PIC ICW3 Init. Cmd Word 3
Register
Master PIC ICW4 Init. Cmd Word 4
Register
Master PIC OCW1 Op Ctrl Word 1
Register
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10–1Fh
20h
21h
Datasheet Section and Location
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-299
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-300
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-299
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-300
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-299
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-300
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-299
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-300
Section 9.2.4, “DMACMD—DMA Command Register”
on page 9-301
Section 9.2.5, “DMASTA—DMA Status Register” on
page 9-301
Section 9.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 9-302
Section 9.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 9-302
Section 9.2.8, “DMA Clear Byte Pointer Register” on
page 9-303
Section 9.2.9, “DMA Master Clear Register” on
page 9-303
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask
Register” on page 9-303
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 9-304
Section 9.4.2, “ICW1—Initialization Command Word 1
Register” on page 9-309
Section 9.4.8, “OCW2—Operational Control Word 2
Register” on page 9-312
Section 9.4.9, “OCW3—Operational Control Word 3
Register” on page 9-313
Section 9.4.3, “ICW2—Initialization Command Word 2
Register” on page 9-310
Section 9.4.4, “ICW3—Master Controller Initialization
Command Word 3 Register” on page 9-310
Section 9.4.6, “ICW4—Initialization Command Word 4
Register” on page 9-311
Section 9.4.7, “OCW1—Operational Control Word 1
(Interrupt Mask) Register” on page 9-311
Intel^® 82801CA ICH3-S Datasheet
503