82801CA Datasheet, PDF (433/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Modem Controller Registers (D31:F6)
14.1.4
14.1.5
14.1.6
PCISTA—Device Status Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
06–07h
0280h
No
Attribute:
Size:
Power Well:
R/WC
16 bits
Core
PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
Description
15 Detected Parity Error (DPE)—RO. Not implemented. Hardwired to 0.
14 Signaled System Error (SSE)—RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS)—R/WC.
13 _{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Bus Master AC ’97 interface function, as a master, generates a master abort.
12 Reserved. Read as 0.
11 Signaled Target Abort (STA)—RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS)—RO. This 2-bit field reflects the ICH3's DEVSEL# timing
10:9 parameter. These read only bits indicate the ICH3's DEVSEL# timing when performing a positive
decode.
8 Data Parity Error Detected (DPED)—RO. Not implemented. Hardwired to 0.
7
Fast Back to Back (FB2B)—RO. Hardwired to 1. This bit indicates that the ICH3 as a target is
capable of fast back-to-back transactions.
6 User Definable Features (UDF)—RO. Not implemented. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
4:0 Reserved. Read as 0's.
RID—Revision Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
08h
See Note
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
Bit
Description
7:0
Revision Identification Value—RO.
NOTE: Refer to the Specification Update for the Revision ID.
PI—Programming Interface Register (Modem—D31:F6)
Address Offset: 09h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Bit
Description
7:0 Programming Interface Value—RO.
Intel^® 82801CA ICH3-S Datasheet
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