82801CA Datasheet, PDF (261/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.3
CMD—Command Register (HUB-PCI—D30:F0)
Offset Address: 04–05h
Default Value: 0001h
Attribute:
Size:
R/W
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
Fast Back to Back Enable (FBE)—RO. Hardwired to 0. The ICH3 does not support this capability.
SERR# Enable (SERR_EN)—R/W.
0 = Disable
1 = Enable the ICH3 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
(offset 06h, bit 14) is set.
Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = The ICH3 will ignore parity errors on the hub interface.
1 = The ICH3 is allowed to report parity errors detected on the hub interface.
VGA Palette Snoop (VPS)—RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.
Special Cycle Enable (SCE)—RO. Hardwired to 0 by P2P Bridge spec.
Bus Master Enable (BME)—R/W.
0 = Disable
1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface.
Note: This bit does not affect the CF8h and CFCh I/O accesses.
NOTE: Cycles that generated from the ICH3’s Device 31 functionality are not blocked by clearing
this bit. (PC/PCI Cascade Mode cycles may be blocked).
Memory Space Enable (MSE)—R/W. The ICH3 provides this bit as read/writable for software only.
However, the ICH3 ignores the programming of this bit, and runs hub interface memory cycles to
PCI.
I/O Space Enable (IOE)—R/W. The ICH3 provides this bit as read/writable for software only.
However, the ICH3 ignores the programming of this bit and runs hub interface I/O cycles to PCI that
are not intended for USB, IDE, or AC ’97.
Intel^® 82801CA ICH3-S Datasheet
261