82801CA Datasheet, PDF (247/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LAN Controller Registers (B1:D8:F0)
7.2.2
System Control Block Command Word Register
Offset Address: 02–03h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
The processor places commands for the Command and Receive units in this register. Interrupts are
also acknowledged in this register.
Bit
Description
CX Mask —R/W.
15 _{0 = Interrupt not masked.}
1 = Disable the generation of a CX interrupt.
FR Mask —R/W.
14 _{0 = Interrupt not masked.}
1 = Disable the generation of an FR interrupt.
CNA Mask —R/W.
13 _{0 = Interrupt not masked.}
1 = Disable the generation of a CNA interrupt.
RNR Mask —R/W.
12 _{0 = Interrupt not masked.}
1 = Disable the generation of an RNR interrupt.
ER Mask —R/W.
11 _{0 = Interrupt not masked.}
1 = Disable the generation of an ER interrupt.
FCP Mask —R/W.
10 _{0 = Interrupt not masked.}
1 = Disable the generation of an FCP interrupt.
Software Generated Interrupt (SI)—WO.
9 _{0 = No Effect.}
1 = Setting this bit causes the LAN Controller to generate an interrupt.
Interrupt Mask (M)—R/W. This bit enables or disables the LAN Controllers assertion of the INTA#
signal. This bit has higher precedence that the specific interrupt mask bits and the SI bit.
8
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
Intel^® 82801CA ICH3-S Datasheet
247