82801CA Datasheet, PDF (407/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.3
12.2.4
12.2.5
12.2.6
HST_CMD—Host Command Register
Register Offset: 03h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
This eight bit field is transmitted by the host controller in the command field of the SMBus protocol
during the execution of any command.
XMIT_SLVA—Transmit Slave Address Register
Register Offset: 04h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
Bit
Description
7:1 Address—R/W. 7-bit address of the targeted slave.
Read/Write Control (RW)—R/W. Direction of the host transfer.
0 _{0 = Write.}
1 = Read.
HST_D0—Data 0 Register
Register Offset: 05h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
DATA0/COUNT—R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus
7:0
protocol. For block write commands, this register reflects the number of bytes to transfer. This register
should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32
will result in unpredictable behavior. The host controller does not check or log illegal block counts.
HST_D1—Data 1 Register
Register Offset: 06h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
DATA1—R/W. This eight bit register is transmitted in the DATA1 field of the SMBus protocol during
the execution of any command.
Intel^® 82801CA ICH3-S Datasheet
407