82801CA Datasheet, PDF (25/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

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Token Format...............................................................................................187
SOF Packet..................................................................................................187
Data Packet Format .....................................................................................188
Bits Maintained in Low Power States...........................................................191
USB Legacy Keyboard State Transitions.....................................................193
Quick Protocol..............................................................................................195
Send / Receive Byte Protocol without PEC .................................................196
Send/Receive byte Protocol with PEC.........................................................196
Write Byte/Word Protocol without PEC........................................................197
Write Byte/Word Protocol with PEC.............................................................197
Read Byte/Word Protocol without PEC........................................................198
Read Byte/Word Protocol with PEC.............................................................199
Process Call Protocol without PEC..............................................................200
Process Call Protocol with PEC...................................................................201
Block Read/Write Protocol without PEC ......................................................202
Block Read/Write Protocol with PEC ...........................................................203
Enable for SMBALERT# ..............................................................................205
Enables for SMBus Slave Write and SMBus Host Events...........................205
Enables for the Host Notify Command.........................................................205
Slave Write Cycle Format ............................................................................207
Slave Write Registers ..................................................................................207
Command Types..........................................................................................208
Read Cycle Format ......................................................................................209
Data Values for Slave Read Registers ........................................................210
Host Notify Format .......................................................................................211
Features Supported by Intel^® ICH3 .............................................................212
AC ’97 Signals .............................................................................................214
Input Slot 1 Bit Definitions............................................................................220
Output Tag Slot 0.........................................................................................222
AC-Link State during PCIRST#....................................................................225
PCI Devices and Functions..........................................................................228
Intel^® ICH3 Device IDs ................................................................................229
Fixed I/O Ranges Decoded by Intel^® ICH3..................................................230
Variable I/O Decode Ranges .......................................................................232
Memory Decode Ranges from Processor Perspective ................................233
PCI Configuration Map (LAN Controller—B1:D8:F0)...................................235
Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ...240
Data Register Structure ...............................................................................244
Intel^® ICH3 Integrated LAN Controller CSR Space .....................................245
Self-Test Results Format .............................................................................250
Statistical Counters ......................................................................................255
PCI Configuration Map (HUB-PCI—D30:F0) ...............................................259
PCI Configuration Map (LPC I/F—D31:F0)..................................................275
DMA Registers.............................................................................................298
PIC Registers...............................................................................................308
APIC Direct Registers ..................................................................................316
APIC Indirect Registers................................................................................316
RTC I/O Registers........................................................................................322
RTC (Standard) RAM Bank .........................................................................323
PCI Configuration Map (PM—D31:F0) ........................................................330
APM Register Map.......................................................................................335
Intel^® 82801CA ICH3-S Datasheet
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