82801CA Datasheet, PDF (152/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.11 System Power Supplies, Planes, and Signals
5.12.11.1 Power Plane Control with SLP_S3# and SLP_S5#
The SLP_S3# output signal can be used to cut power to the system core supply, since it will only go
active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH3
Resume Well, and to any other circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard. The SLP_S5# output signal can be used to cut power to the system core supply, as
well as power to the system memory, since the context of the system is saved on the disk. Cutting
power to the memory may be done via the power supply, or by external FETs to the motherboard.
5.12.11.2 PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid. PWROK
should go active no sooner than 10 ms after Vcc3_3 and Vcc1_8 have reached their nominal
values.
Notes:
1. Traditional designs have a reset button logically ANDs with the PWROK signal from the
power supply and the processor’s voltage regulator module. If this is done with the ICH3, the
PWROK_FLR bit will be set. The ICH3 treats this internally as if the RSMRST# signal had
gone active. However, it is not treated as a full power failure. If PWROK goes inactive and
then active (but RSMRST# stays high), then the ICH3 will reboot (regardless of the state of
the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this
is a full power failure, and the reboot policy is controlled by the AFTERG3 bit.
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less
than one RTC clock period may not be detected by the ICH3
5.12.11.3 VRMPWRGD Signal
This signal is connected to the processor’s VRM and is internally ANDed with the PWROK signal
that comes from the system power supply. This saves the external AND gate found in server
systems that traditionally has been external to the chipset.
5.12.11.4 Controlling Leakage and Power Consumption During Low-Power
States
To control leakage in the system, various signals will tri-state or go low during some low-power
states.
General principles
• All signals going to powered down planes (either internally or externally) must be either tri-
stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to avoid the
power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some
other device). Floating inputs can cause extra power consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.
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Intel^® 82801CA ICH3-S Datasheet