82801CA Datasheet, PDF (163/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-52. IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)
I/O Offset
00h
01h
02h
03h
04h
05h
06h
07h
Register Function (Read)
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive
Status
Register Function (Write)
Data
Features
Sector Count
Sector Number
Cylinder Low
Cylinder High
Head
Command
Table 5-53. IDE Legacy I/O Ports: Control Block Registers (CS3x# Chip Select)
I/O Offset
00h
01h
02h
03h
Register Function (Read)
Reserved
Reserved
Alt Status
Forward to LPC–Not claimed by IDE
Register Function (Write)
Reserved
Reserved
Device control
Forward to LPC–Not claimed by IDE
NOTE: For accesses to the alt status register in the Control Block, the ICH3 must always force the upper
address bit (PDA[2] or SDA[2]) to 1 in order to guarantee proper native mode decode by the IDE device.
Unlike the legacy mode fixed address location, the native mode address for this register may contain a 0
in address bit 2 when it is received by the ICH3
In native mode, the ICH3 does not decode the legacy ranges. The same offsets are used as in
Table 5-52 and Table 5-53 above. However, the base addresses are selected using the PCI BARs,
rather than fixed I/O locations.
5.15.1.3
PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency.
Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the
DA[2:0] and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0]
and CSxx# lines prior to assertion of the read and write strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery
time is provided so that transactions may occur back-to-back on the IDE interface (without
incurring startup and shutdown latency) without violating minimum cycle periods for the IDE
interface. The command strobe assertion width for the enhanced timing mode is selected by the
IDE_TIM Register and may be set to 2, 3, 4, or 5 PCI clocks. The recovery time is selected by the
IDE_TIM Register and may be set to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait-states are added to the
command strobe assertion length. If IORDY is negated when the initial sample point is reached,
additional wait-states are added. Since the rising edge of IORDY must be synchronized, at least
two additional PCI clocks are added.
Intel^® 82801CA ICH3-S Datasheet
163