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82801CA Datasheet, PDF (314/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S) | |||
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LPC I/F Bridge Registers (D31:F0)
9.4.10
ELCR1âMaster Controller Edge/Level Triggered Register
Offset Address: 4D0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat
timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit
IRQ7 ECLâR/W.
7 0 = Edge.
1 = Level.
IRQ6 ECLâR/W.
6 0 = Edge.
1 = Level.
IRQ5 ECLâR/W.
5 0 = Edge.
1 = Level.
IRQ4 ECLâR/W.
4 0 = Edge.
1 = Level.
IRQ3 ECLâR/W.
3 0 = Edge.
1 = Level.
2:0 Reserved. Must be 0.
Description
314
Intel® 82801CA ICH3-S Datasheet
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