82801CA Datasheet, PDF (328/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register
I/O Address:
70h
Default Value: 80h
Lockable:
No
Attribute:
Size:
Power Well:
R/W (Special)
8-bit
Core
Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-Access
Mode. Note, however that this register is aliased to Port 74h (documented in Table 9-6), and all bits
are readable at that address.
Bits
Description
NMI Enable (NMI_EN)—R/W.
7
0 = Enable NMI sources.
1 = Disable All NMI sources.
6:0
Real Time Clock Index Address (RTC_INDX)—R/W. This data goes to the RTC to select which
register or CMOS RAM address is being accessed.
9.7.3
PORT92—Fast A20 and Init Register
I/O Address:
92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:2 Reserved.
Alternate A20 Gate (ALT_A20_GATE)—R/W. This bit is Or’d with the A20GATE input signal to
generate A20M# to the processor.
1
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
0
INIT_NOW—R/W. When this bit transitions from a 0 to a 1, the ICH3 will force INIT# active for 16
PCI clocks.
9.7.4
COPROC_ERR—Coprocessor Error Register
I/O Address:
F0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
WO
8-bits
Core
Bits
Description
COPROC_ERR—WO. Any value written to this register will cause IGNNE# to go active, if FERR#
7:0 had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the
COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, Bit 13) must be 1.
328
Intel^® 82801CA ICH3-S Datasheet