82801CA Datasheet, PDF (305/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.3
Timer I/O Registers
9.3.1
Port
40h
41h
42h
43h
Aliases
50h
51h
52h
53h
Register Name
Counter 0 Interval Time Status Byte Format
Counter 0 Counter Access Port
Counter 1 Interval Time Status Byte Format
Counter 1 Counter Access Port
Counter 2 Interval Time Status Byte Format
Counter 2 Counter Access Port
Timer Control Word
Timer Control Word Register Read Back
Counter Latch Command
Default Value
0XXXXXXXb
Undefined
0XXXXXXXb
Undefined
0XXXXXXXb
Undefined
Undefined
XXXXXXX0b
X0h
Type
RO
R/W
RO
R/W
RO
R/W
WO
WO
WO
TCW—Timer Control Word Register
I/O Address:
Default Value:
43h
All bits undefined
Attribute:
Size:
WO
8 bits
This register is programmed prior to any counter being accessed to specify counter modes.
Following part reset, the control words for each register are undefined and each counter output is 0.
Each timer must be programmed to bring it into a known state.
Bit
Description
Counter Select—WO. The Counter Selection bits select the counter the control word acts upon as
shown below. The Read Back Command is selected when bits[7:6] are both 1.
00 = Counter 0 select
7:6 _{01 = Counter 1 select}
10 = Counter 2 select
11 = Read Back Command
Read/Write Select—WO. These bits are the read/write control bits. The actual counter programming
is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2).
00 = Counter Latch Command
5:4 _{01 = Read/Write Least Significant Byte (LSB)}
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Counter Mode Selection—WO. These bits select one of six possible modes of operation for the
selected counter.
000 = Mode 0Out signal on end of count (=0)
001 = Mode 1Hardware retriggerable one-shot
3:1 _{x10 = Mode 2Rate generator (divide by n counter)}
x11 = Mode 3Square wave output
100 = Mode 4Software triggered strobe
101 = Mode 5Hardware triggered strobe
Binary/BCD Countdown Select—WO.
0 _{0 = Binary countdown is used. The largest possible binary count is 216.}
1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104.
There are two special commands that can be issued to the counters through this register, the Read
Back Command and the Counter Latch Command. When these commands are chosen, several bits
within this register are redefined. These register formats are described below.
Intel^® 82801CA ICH3-S Datasheet
305