82801CA Datasheet, PDF (20/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

14.2 AC ’97 Modem I/O Space (D31:F6)............................................................. 437
14.2.1 x_BDBAR—Buffer Descriptor List Base Address Register............. 439
14.2.2 x_CIV—Current Index Value Register ............................................ 439
14.2.3 x_LVI—Last Valid Index Register ................................................... 439
14.2.4 x_SR—Status Register ................................................................... 440
14.2.5 x_PICB—Position In Current Buffer Register ................................. 441
14.2.6 x_PIV—Prefetch Index Value Register ........................................... 441
14.2.7 x_CR—Control Register ................................................................. 442
14.2.8 GLOB_CNT—Global Control Register............................................ 443
14.2.9 GLOB_STA—Global Status Register ............................................. 444
14.2.10 CAS—Codec Access Semaphore Register .................................... 445
15
Ballout Definition .............................................................................................. 447
16
Electrical Characteristics .............................................................................. 457
16.1 Absolute Maximum Ratings ......................................................................... 457
16.2 Functional Operating Range........................................................................ 457
16.3 DC Characteristics....................................................................................... 458
16.4 AC Characteristics ....................................................................................... 464
16.5 Timing Diagrams.......................................................................................... 475
17
Package Information ....................................................................................... 485
18
Testability ............................................................................................................ 487
18.1 Test Mode Description................................................................................. 487
18.2 Tri-state Mode.............................................................................................. 488
18.3 XOR Chain Mode......................................................................................... 488
18.3.1 XOR Chain Testability Algorithm Example ..................................... 488
A
Register Index .................................................................................................... 495
B
Register Bit Index ............................................................................................. 515
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Intel^® 82801CA ICH3-S Datasheet