82801CA Datasheet, PDF (41/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Signal Description
Table 2-5. PCI Interface Signals (Continued)
Name
IRDY#
TRDY#
STOP#
PAR
PERR#
REQ[4:0]#
REQ[5]# /
REQ[B]# /
GPIO[1]
GNT[4:0]#
GNT[5]# /
GNT[B]# /
GPIO[17]#
PCICLK
PCIRST#
Type
Description
Initiator Ready: IRDY# indicates the ICH3's ability, as an Initiator, to complete the
current data phase of the transaction. It is used in conjunction with TRDY#. A data
phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
I/O During a write, IRDY# indicates the ICH3 has valid data present on AD[31:0].
During a read, it indicates the ICH3 is prepared to latch data. IRDY# is an input to
the ICH3 when the ICH3 is the Target and an output from the ICH3 when the ICH3
is an Initiator. IRDY# remains tri-stated by the ICH3 until driven by an Initiator.
Target Ready: TRDY# indicates the ICH3's ability as a Target to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A
data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH3, as a Target, has placed valid data
I/O on AD[31:0]. During a write, TRDY# indicates the ICH3, as a Target is prepared to
latch data. TRDY# is an input to the ICH3 when the ICH3 is the Initiator and an
output from the ICH3 when the ICH3 is a Target. TRDY# is tri-stated from the
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH3 until driven by a
target.
Stop: STOP# indicates that the ICH3, as a Target, is requesting the Initiator to
stop the current transaction. STOP# causes the ICH3, as an Initiator, to stop the
I/O current transaction. STOP# is an output when the ICH3 is a Target and an input
when the ICH3 is an Initiator. STOP# is tri-stated from the leading edge of
PCIRST#. STOP# remains tri-stated until driven by the ICH3.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH3 counts the number of
“1”s within the 36 bits plus PAR and the sum is always even. The ICH3 always
calculates PAR on 36 bits regardless of the valid byte enables. The ICH3
generates PAR for address and data phases and only guarantees PAR to be valid
one PCI clock after the corresponding address or data phase. The ICH3 drives
I/O
and tri-states PAR identically to the AD[31:0] lines except that the ICH3 delays
PAR by exactly one PCI clock. PAR is an output during the address phase
(delayed one clock) for all ICH3 initiated transactions. PAR is an output during the
data phase (delayed one clock) when the ICH3 is the Initiator of a PCI write
transaction, and when it is the Target of a read transaction. ICH3 checks parity
when it is the Target of a PCI write transaction. If a parity error is detected, the
ICH3 will set the appropriate internal status bits, and has the option to generate an
NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives data that has
I/O
a parity error. The ICH3 drives PERR# when it detects a parity error. The ICH3 can
either generate an NMI# or SMI# upon detecting a parity error (either detected
internally or reported via the PERR# signal).
PCI Requests: Supports up to 6 masters on the PCI bus. REQ[5]# is muxed with
PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI
I ^{or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1].}
NOTE: REQ[0]# is programmable to have improved arbitration latency for
supporting PCI-based 1394 controllers.
PCI Grants: Supports up to 6 masters on the PCI bus. GNT[5]# is muxed with PC/
PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI or
PC/PCI, GNT[5]# can instead be used as a GPIO.
O
Pull-up resistors are not required on these signals. If pull-ups are used, they
should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an
internal pull-up.
PCI Clock: 33 MHz clock. PCICLK provides timing for all transactions on the PCI
I ^Bus.
NOTE:
PCI Reset: ICH3 asserts PCIRST# to reset devices that reside on the PCI bus.
The ICH3 asserts PCIRST# during power-up and when S/W initiates a hard reset
O sequence through the RC (CF9h) Register. The ICH3 drives PCIRST# inactive a
minimum of 1 ms after PWROK is driven active. The ICH3 drives PCIRST# active
a minimum of 1 ms when initiated through the RC Register.
Intel^® 82801CA ICH3-S Datasheet
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