82801CA Datasheet, PDF (327/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.7
9.7.1
Processor Interface Registers
NMI_SC—NMI Status and Control Register
I/O Address:
61h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W (some bits RO)
8-bit
Core
Bit
Description
SERR# NMI Source Status (SERR#_NMI_STS)—RO.
7
1 = PCI agent detected a system error and pulses the PCI SERR# line. This interrupt source is
enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing
to port 61h, this bit must be 0.
IOCHK# NMI Source Status (IOCHK_NMI_STS)—RO.
6
1 = An ISA agent (via SERIRQ) asserted IOCHK# on the ISA bus. This interrupt source is enabled
by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to 1. When writing to port
61h, this bit must be a 0.
Timer Counter 2 OUT Status (TMR2_OUT_STS)—RO. This bit reflects the current state of the 8254
5 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a
determinate value. When writing to port 61h, this bit must be a 0.
4
Refresh Cycle Toggle (REF_TOGGLE)—RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate
that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN)—R/W.
3 _{0 = Enabled.}
1 = Disabled and cleared.
PCI SERR# Enable (PCI_SERR_EN)—R/W.
2 _{0 = SERR# NMIs are enabled.}
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable (SPKR_DAT_EN)—R/W.
1 _{0 = SPKR output is a 0.}
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN)—R/W.
0 _{0 = Disable.}
1 = Enable.
Intel^® 82801CA ICH3-S Datasheet
327