82801CA Datasheet, PDF (201/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-85. Process Call Protocol with PEC
Bit
1
2–8
9
10
11–18
19
20–27
28
29–36
37
38
39–45
46
47
48–55
56
57–64
65
66–73
74
75
Description
Start
Slave Address–7 bits
Write
Acknowledge from Slave
Command code–8 bits
Acknowledge from slave
Data byte Low–8 bits
Acknowledge from slave
Data Byte High–8 bits
Acknowledge from slave
Repeated Start
Slave Address–7 bits
Read
Acknowledge from slave
Data Byte Low from slave–8 bits
Acknowledge
Data Byte High from slave–8 bits
Acknowledge
PEC from slave
NOT acknowledge
Stop
Block Read/Write
The Block Write begins with a slave address and a write condition. After the command code, the
ICH3 issues a byte count which describes how many more bytes will follow in the message. If a
slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of
data. The byte count may not be 0.
Note that, unlike the PIIX4, which implements 32-byte buffer for Block Read/Write command, the
ICH3 implements the block data byte register (D31:F3, I/O offset 07h) for Block Read/Write
command.
When programmed for a Block Write command, the Transmit Slave Address, Host Command, and
Data 0 (count) Registers are sent. Data is then sent from the block data byte register. After the byte
has been sent, the ICH3 will set the BYTE_DONE_STS bit in the Host Status Register. If there are
more bytes to send, the software will write the next byte to the block data byte register and will also
clear the BYTE_DONE_STS bit. The ICH3 will then send the next byte. When doing a block
write, first poll the BYTE_DONE_STS Register until it is set, then write the next byte, then clear
the BYTE_DONE_STS Register.
On block read commands, after the byte count is stored in the Data 0 Register, the first data byte
goes in the block data byte register; the ICH3 will then set the BYTE_DONE_STS bit and generate
an SMI# or interrupt. The SMI# or interrupt handler will read the byte and then clear the
BYTE_DONE_STS bit to allow the next byte to be read into the block data byte register. Note that
Intel^® 82801CA ICH3-S Datasheet
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