82801CA Datasheet, PDF (311/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.4.5
9.4.6
9.4.7
ICW3—Slave Controller Initialization Command Word 3
Register
Offset Address: A1h
Default Value: All bits undefined
Attribute:
Size:
WO
8 bits
Bit
Description
7:3 0 = These bits must be programmed to zero.
Slave Identification Code—WO. These bits are compared against the slave identification code
broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing
2:0 edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code
broadcast by the master controller. When 02h is broadcast by the master controller during the INTA#
sequence, the slave controller assumes responsibility for broadcasting the interrupt vector.
ICW4—Initialization Command Word 4 Register
Offset Address:
Default Value:
Master Controller–021h
Slave Controller–0A1h
Attribute:
Size:
WO
8 bits
Bit
Description
7:5 0 = These bits must be programmed to zero.
Special Fully Nested Mode (SFNM)—WO.
4 _{0 = Should normally be disabled by writing a 0 to this bit.}
1 = Special fully nested mode is programmed.
Buffered Mode (BUF)—WO.
3
0 = Must be programmed to 0 for the ICH3. This is non-buffered mode.
Master/Slave in Buffered Mode—WO. Not used.
2
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI)—WO.
1 _{0 = This bit should normally be programmed to 0. This is the normal end of interrupt.}
1 = Automatic End of Interrupt (AEOI) mode is programmed. AEOI is discussed in Section 5.7.4.10.
Microprocessor Mode—WO.
0 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-
based system.
OCW1—Operational Control Word 1 (Interrupt Mask)
Register
Offset Address:
Default Value:
Master Controller–021h
Slave Controller–0A1h
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Interrupt Request Mask—R/W. When a 1 is written to any bit in this register, the corresponding IRQ
7:0
line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is
cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master
controller will also mask the interrupt requests from the slave controller.
Intel^® 82801CA ICH3-S Datasheet
311