82801CA Datasheet, PDF (361/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.10.3
9.10.4
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +04h
0000FFFFh
No
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
Description
31:29, 26 Reserved.
28:27
25:24
GPIO[n]_SEL—R/W.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
23:16 Always 0. The GPIOs are fixed as outputs.
15:0 Always 1. These GPIOs are fixed as inputs.
GP_LVL—GPIO Level for Input or Output Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +0Ch
1B3F 0000h
No
Attribute:
Size:
Power Well:
R/W, RO
32-bit
See bit descriptions
Bit
Description
31:29, 26 Reserved.
28:27,
25:24
GP_LVL[n]—R/W. If GPIO[n] is programmed to be an output (via the corresponding bit in the
GP_IO_SEL register) then the bit can be updated by software to drive a high or low value on the
output pin. If GPIO[n] is programmed as an input, then software can read the bit to determine the
level on the corresponding input pin. These bits correspond to GPIO that are in the Resume well,
and will be reset to their default values by RSMRST# but not by PCIRST#.
0 = Low
1 = High
23:16
GP_LVL[n]—R/W. These bits can be updated by software to drive a high or low value on the
output pin. These bits correspond to GPIO that are in the Core well, and will be reset to their
default values by PCIRST#.
0 = Low
1 = High
15:0
Reserved. GPI[13:11] and [8:0] the active status of a GPI is read from the corresponding bit in
GPE1_STS register.
Intel^® 82801CA ICH3-S Datasheet
361