82801CA Datasheet, PDF (419/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.1.15
INTR_PN—Interrupt Pin Register (Audio—D31:F5)
Address Offset: 3Dh
Default Value: 02h
Lockable:
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
This register indicates which PCI interrupt pin is used for the AC ’97 module interrupt. The AC ’97
interrupt is internally OR’ed to the interrupt controller with the PIRQB# signal.
Bit
Description
7:3 Reserved.
2:0 Interrupt Pin (INT_PN)—RO. Hardwired to 010b to select PIRQB#.
13.1.16 PCID—Programmable Codec ID Register (Audio—D31:F5)
Address Offset: 40h
Default Value: 01h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Note: The value in this register must only be modified prior to any AC ’97 codec accesses.
Bit
Description
7:2 Reserved.
Secondary Codec ID (SCID)—R/W. These two bits define the encoded ID that is used to address
1:0
the secondary codec I/O space. The two bits are the ID that will be placed on slot-0, bits 0 and 1,
upon an I/O access to the secondary codec. Bit 1 is the first bit sent and bit 0 is the second bit sent
on AC_SDATA_OUT during slot 0.
Intel^® 82801CA ICH3-S Datasheet
419