82801CA Datasheet, PDF (146/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.8 Thermal Management
The ICH3 has mechanisms to assist with managing thermal problems in the system.
5.12.8.1
THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM# signal
going active, the ICH3 generates an SMI# or SCI (depending on SCI_EN).
If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit will be
set. This is an indicator that the thermal threshold has been exceeded. If the THRM_EN bit is set,
then when THRM_STS goes active, either an SMI# or SCI will be generated (depending on the
SCI_EN bit being set).
The power management software (BIOS or ACPI) can then take measures to start reducing the
temperature. Examples include shutting off unwanted subsystems, or halting the processor.
By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated when the
THRM# signal goes back high. This allows the software (BIOS or ACPI) to turn off the cooling
methods.
Note: THRM# assertion will not cause TCO event message in S3 or S4. The level of the signal will not
be reported in the heartbeat message.
5.12.8.2
THRM# Initiated Passive Cooling
If the THRM# signal remains active for some time greater than 2 seconds and the ICH3 is in the
S0/G0/C0 state, then the ICH3 enters an auto-throttling mode, in which it provides a duty cycle on
the STPCLK# signal. This will reduce the overall power consumption by the system, and should
cool the system. The intended result of the cooling is that the THRM# signal should go back
inactive.
For all programmed values (001–111), THRM# going active will result in STPCLK# active for a
minimum time of 12.5% and a maximum of 87.5%. The period is 1024 PCI clocks. Thus, the
STPCLK# signal can be active for as little as 128 PCI clocks or as much as 896 PCI clocks. The
actual slowdown (and cooling) of the processor will depend on the instruction stream, because the
processor is allowed to finish the current instruction. Furthermore, the ICH3 waits for the STOP-
GRANT cycle before starting the count of the time the STPCLK# signal is active.
When THRM# goes inactive, the throttling will stop.
In case that the ICH3 is already attempting throttling because the THTL_EN bit is set, the duty
cycle associated with the THRM# signal will have higher priority.
If the ICH3 is in the C2 or S1–S5 states, then no throttling will be caused by the THRM# signal
being active.
5.12.8.3
THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, just as if the THRM# signal had
been active for 2 seconds. If this bit is set, the ICH3 will start throttling using the ratio in the
THRM_DTY field.
When this bit is cleared the ICH3 will stop throttling, unless the THRM# signal has been active for
2 seconds or if the THTL_EN bit is set (indicating that ACPI software is attempting throttling).
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Intel^® 82801CA ICH3-S Datasheet