82801CA Datasheet, PDF (371/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

IDE Controller Registers (D31:F1)
10.1.16
IDE_SVID—Subsystem Vendor ID Register (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
00h
No
Attribute:
Size:
Power Well:
R/Write-Once
16 bits
Core
Bit
Description
Subsystem Vendor ID—R/WO. The SVID register, in combination with the Subsystem ID (SID)
register, enables the operating system (OS) to distinguish subsystems from each other. Software
15:0 (BIOS) sets the value in this register. After that, the value can be read, but subsequent writes to this
register have no effect. The value written to this register will also be readable via the corresponding
SVID registers for the USB#1, USB#2 and SMBus functions.
10.1.17
IDE_SID—Subsystem ID Register (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
R/Write-Once
16 bits
Core
Bit
Description
Subsystem ID—R/WO. The SID register, in combination with the SVID register, enables the
operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in
15:0 this register. After that, the value can be read, but subsequent writes to this register have no effect.
The value written to this register will also be readable via the corresponding SID registers for the
USB#1, USB#2 and SMBus functions.
10.1.18
INTR_LN—Interrupt Line Register (IDE—D31:F1)
Address Offset: 3Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt Line (INT_LN). It is to communicate to software the interrupt line that the interrupt pin is
connected to.
10.1.19
INTR_PN—Interrupt Pin Register (IDE—D31:F1)
Address Offset: 3Dh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Reserved.
Interrupt Pin (INT_PN). The value of 01h indicates to “software” that the ICH3 will drive PIRQ[A]#.
2:0
Note that this is only used in native mode. Also note that the routing to the internal interrupt
controller does not necessarily relate to the value in this register. The IDE interrupt is in fact routed
to PIRQ[C]# (IRQ18 in APIC mode). Read-Only.
Intel^® 82801CA ICH3-S Datasheet
371