82801CA Datasheet, PDF (91/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.3.1.11 LPC Power Management
5.3.1.12
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drives LDRQ#
low or tri-state it. The ICH3 shuts off the LDRQ# input buffers. After driving SUS_STAT# active,
the ICH3 drives LFRAME# low and tri-states (or drive low) LAD[3:0].
Configuration and Intel^® ICH3 Implications
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC I/F, the ICH3 includes several
decoders. During configuration, the ICH3 must be programmed with the same decode ranges as the
peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.
Note:
The ICH3 can not accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device
if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are
not part of normal system operation, but may be encountered as part of platform validation testing
using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the ICH3 that supports 2 LPC bus
masters, it will drive 0010 for the START field for grants to bus master #0 (requested via
LDRQ[0]#) and 0011 for grants to bus master #1 (requested via LDRQ[1]#.). Thus, no registers are
needed to configure the START fields for a particular bus master.
5.4
DMA Operation (D31:F0)
The ICH3 supports two types of DMA: LPC and PC/PCI. DMA via LPC is similar to ISA DMA.
LPC DMA and PC/PCI DMA use the ICH3’s DMA controller.
The DMA controller has registers that are fixed in the lower 64 KB of I/O space.
The DMA controller is configured using registers in the PCI configuration space. These registers
allow configuration of individual channels for use by LPC or PC/PCI DMA.
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven
independently programmable channels (Figure 5-9). DMA Controller 1 (DMA-1) corresponds to
DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to Channels 5–7. DMA Channel
4 is used to cascade the two controllers and will default to cascade mode in the DMA Channel
Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting
requests from DMA slaves, the DMA controller also responds to requests that software initiates.
Software may initiate a DMA service request by setting any bit in the DMA Channel Request
Register to a 1.
Intel^® 82801CA ICH3-S Datasheet
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