82801CA Datasheet, PDF (387/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

USB 1.1 Controllers Registers
Bit
Description
SMI Caused by USB Interrupt (SMIBYUSB)—RO. Indicates if an interrupt event occurred from this
controller. The interrupt from the controller is taken before the enable in bit 13 has any effect to create
this read-only bit. Note that even if the corresponding enable bit is not set in the Bit 4, then this bit may
12 still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software should clear the interrupts via the USB controllers. Writing a 1 to this bit will have no
effect.
1 = Event Occurred.
SMI Caused by Port 64 Write (TRAPBY64W)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the
11
SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate
Pass-Through Logic allows specific port 64h writes to complete without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 64 Read (TRAPBY64R)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the
10 SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Write (TRAPBY60W)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate
9 _{Pass-Through Logic allows specific port 64h writes to complete without setting this bit.}
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Read (TRAPBY60R)—R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the
8 ^{SMM code to use the enable bit to determine the exact cause of the SMI#.}
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI at End of Pass-through Enable (SMIATENDPS)—R/W. May need to cause SMI at the end of a
pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be
7 serviced later.
0 = Disable.
1 = Enable.
Pass Through State (PSTATE)—RO.
6 _{0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.}
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
A20Gate Pass-Through Enable (A20PASSEN)—R/W.
5 ^{0 = Disable.}
1 = Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to
port 60h and 64h does not result in the setting of the SMI status bits.
SMI on USB IRQ Enable (USBSMIEN)—R/W.
4 0 = Disable
1 = USB interrupt will cause an SMI event..
SMI on Port 64 Writes Enable (64WEN)—R/W.
3 _{0 = Disable.}
1 = A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN)—R/W.
2 0 = Disable.
1 = A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN)—R/W.
1 _{0 = Disable.}
1 = A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN)—R/W.
0 0 = Disable.
1 = A 1 in bit 8 will cause an SMI event.
Intel^® 82801CA ICH3-S Datasheet
387