82801CA Datasheet, PDF (270/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.25
8.1.26
BRIDGE_CNT2—Bridge Control Register 2
(HUB-PCI—D30:F0)
Offset Address: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved.
PCI_DAC_EN—R/W. Allows ICH3 to recognize external PCI masters performing DAC on PCI.
0 _{0 = Disable}
1 = Enable
DEVICE_HIDE—Secondary PCI Device Hiding Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Power Well:
44–45h
00h
00h
Attribute:
Size:
R/W
16 bits
This register allows software to “hide” PCI devices (0 through 5) in terms of configuration space.
Specifically, when PCI devices (0–5) are hidden, the configuration space is not accessible because
the PCI IDSEL pin does not assert. The ICH3 supports the hiding of 6 external devices (0 through
5), which matches the number of PCI request/grant pairs, and the ability to hide the integrated LAN
device by masking out the configuration space decode of LAN controller. Writing a 1 to this bit
will not restrict the configuration cycle to the PCI bus. This differs from bits 0 through 5 in which
the configuration cycle is restricted.
Hiding a PCI device can be useful for debugging, bug work-arounds, and system management
support. Devices should only be hidden during initialization before any configuration cycles are
run. This guarantees that the device is not in a semi-enable state.
Bit
Description
15:9 Reserved.
8
HIDE_DEV8. Same as bit 0 of this register, except for device 8 (AD[24]), which is hardwired to the
integrated LAN device. This bit will not change the way the configuration cycle appears on PCI bus
7:6 Reserved.
5 HIDE_DEV5. Same as bit 0 of this register, except for device 5 (AD[21]).
4 HIDE_DEV4. Same as bit 0 of this register, except for device 4 (AD[20]).
3 HIDE_DEV3. Same as bit 0 of this register, except for device 3 (AD[19]).
2 HIDE_DEV2. Same as bit 0 of this register, except for device 2 (AD[18]).
1 HIDE_DEV1. Same as bit 0 of this register, except for device 1 (AD[17]).
HIDE_DEV0.
0 = The PCI configuration cycles for this slot are not affected.
0
1 = Device 0 hidden on the PCI bus. This is done by masking the IDSEL (keeping it low) for
configuration cycles to that device. Since the device does not see its IDSEL go active, it does
not respond to PCI configuration cycles and the processor thinks the device is not present.
AD[16] is used as IDSEL for device 0.
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Intel^® 82801CA ICH3-S Datasheet