82801CA Datasheet, PDF (75/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Controller controls the TRDY# signal and asserts it from the data access. The LAN Controller
allows the processor to issue only one I/O write cycle to the CSRs, generating a disconnect by
asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
Retry Premature Accesses
The LAN Controller responds with a Retry to any configuration cycle accessing the LAN
Controller before the completion of the automatic read of the EEPROM. The LAN Controller may
continue to Retry any configuration accesses until the EEPROM read is complete. The LAN
Controller does not enforce the rule that the retried master must attempt to access the same address
again in order to complete any delayed transaction. Any master access to the LAN Controller after
the completion of the EEPROM read will be honored.
Error Handling
Data Parity Errors: The LAN Controller checks for data parity errors while it is the target of the
transaction. If an error was detected, the LAN Controller always sets the detected parity error bit in
the PCI configuration status register, bit 15. The LAN Controller also asserts PERR#, if the parity
error response bit is set (PCI configuration command register, bit 6). The LAN Controller does not
attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option
of recovery.
Target-Disconnect: The LAN Controller prematurely terminate a cycle in the following cases:
• After accesses to its CSR
• After accesses to the configuration space
System Error: The LAN Controller reports parity error during the address phase using the SERR#
pin. If the SERR# enable bit in the PCI configuration command register or the parity error response
bit are not set, the LAN Controller only sets the detected parity error bit (PCI configuration status
register, bit 15). If SERR# enable and parity error response bits are both set, the LAN Controller
sets the signaled system error bit (PCI configuration status register, bit 14) as well as the detected
parity error bit and asserts SERR# for one clock.
The LAN Controller, when detecting system error, will claim the cycle if it was the target of the
transaction and continue the transaction as if the address was correct.
Note: The LAN Controller will report a system error for any error during an address phase, whether or
not it is involved in the current transaction.
5.2.3.2
Bus Master Operation
As a PCI Bus Master, the ICH3 integrated LAN Controller initiates memory cycles to fetch data for
transmission or deposit received data and for accessing the memory resident control structures. The
LAN Controller performs zero wait-state burst read and write cycles to the host main memory. For
bus master cycles, the LAN Controller is the initiator and the host main memory (or the PCI host
bridge, depending on the configuration of the system) is the target.
The processor provides the LAN Controller with action commands and pointers to the data buffers
that reside in host main memory. The LAN Controller independently manages these structures and
initiates burst memory cycles to transfer data to and from them. The LAN Controller uses the
Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the
Memory Read Line (MR Line) command for burst accesses to control structures. For all write
Intel^® 82801CA ICH3-S Datasheet
75