82801CA Datasheet, PDF (78/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.2.3.3
If this bit is set, the LAN Controller operates as follows:
• When the LAN Controller is almost out of resources on the transmit DMA (i.e., the transmit
FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line
boundary when possible.
• When the arbitration counter’s feature is enabled (i.e., the Transmit DMA Maximum Byte
Count value is set in the Configure command), the LAN Controller switches to other pending
DMAs on cache line boundary only.
Note the following:
• This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance.
• This feature should be used only when the CLS Register in PCI Configuration space is set to 8
or 16.
• The LAN Controller reads all control data structures (including Receive Buffer Descriptors)
from the first dword (even if it is not required) in order to maintain cache line alignment.
Error Handling
Data Parity Errors: As an initiator, the LAN Controller checks and detects data parity errors that
occur during a transaction. If the parity error response bit is set (PCI configuration command
register, bit 6), the LAN Controller also asserts PERR# and sets the data parity detected bit (PCI
configuration status register, bit 8). In addition, if the error was detected by the LAN Controller
during read cycles, it sets the detected parity error bit (PCI configuration status register, bit 15).
PCI Power Management
Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.2,
is provided in the ICH3 integrated LAN Controller. The LAN Controller supports a large set of
wake-up packets and the capability to wake the system from a low power state on a link status
change. The LAN Controller enables the host system to be in a sleep state and remain virtually
connected to the network.
After a power management event or link status change is detected, the LAN Controller will wake
the host system. The sections below describe these events, the LAN Controller power states, and
estimated power consumption at each power state.
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Intel^® 82801CA ICH3-S Datasheet