82801CA Datasheet, PDF (71/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.2
5.2.1
LAN Controller (B1:D8:F0)
The ICH3’s integrated LAN Controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN Controller to perform high speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high
level commands and perform multiple operations, which lowers processor utilization by off-
loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB
each help prevent data underruns and overruns while waiting for bus accesses. This enables the
integrated LAN Controller to transmit data with minimum interframe spacing (IFS).
The ICH3 integrated LAN Controller can operate in either full duplex or half duplex mode. In full
duplex mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
The integrated LAN Controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration parameters.
From a software perspective, the integrated LAN Controller appears to reside on the secondary side
of the ICH3’s virtual PCI-to-PCI Bridge (see Section 5.1.2). This is typically Bus 1, but may be
assigned a different number, depending upon system configuration.
Feature Summary
• Compliance with Advanced Configuration and Power Interface and PCI Power Management
standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN* (WOL) technology
• Deep power-down mode support
• Support of Wired for Management (WfM), Rev 2.0
• Backward compatible software with Intel 82557, 82558, and 82559
• TCP/UDP checksum off load capabilities
• Support for Intel’s Adaptive Technology
Intel^® 82801CA ICH3-S Datasheet
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