82801CA Datasheet, PDF (511/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Register Index
Table A-3. Intel^® ICH3 Variable I/O Registers (Continued)
Register Name
Offset
Datasheet Section and Location
SMBus I/O Registers at SMB_BASE + Offset
SMB_BASE is set at Section 12.1.8, “SMB_BASE—SMBus Base Address Register (SMBUS—D31:F3)” on
page 12-401
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Block Data Byte
Receive Slave Address
Receive Slave Data
00h
Section 12.2.1, “HST_STS—Host Status Register” on
page 12-405
02h
Section 12.2.2, “HST_CNT—Host Control Register”
on page 12-406
03h
Section 12.2.3, “HST_CMD—Host Command
Register” on page 12-407
04h
Section 12.2.4, “XMIT_SLVA—Transmit Slave
Address Register” on page 12-407
05h
Section 12.2.5, “HST_D0—Data 0 Register” on
page 12-407
06h
Section 12.2.6, “HST_D1—Data 1 Register” on
page 12-407
07h
Section 12.2.7, “BLOCK_DB—Block Data Byte
Register” on page 12-408
09h
Section 12.2.9, “RCV_SLVA—Receive Slave Address
Register” on page 12-408
0Ah
Section 12.2.10, “SLV_DATA—Receive Slave Data
Register” on page 12-409
AC’97 Audio I/O Registers at NAMBAR + Offset
NAMBAR is set at Section 13.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register
(Audio—D31:F5)” on page 13-417
PCM In Buffer Descriptor list Base
Address Register
PCM In Current Index Value
PCM In Last Valid Index
PCM In Status Register
PCM In Position In Current Buffer
PCM In Prefetched Index Value
PCM In Control Register
PCM Out Buffer Descriptor list Base
Address Register
PCM Out Current Index Value
PCM Out Last Valid Index
PCM Out Status Register
PCM Out Position In Current Buffer
00h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-422
04h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-423
05h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-423
06h
Section 13.2.4, “x_SR—Status Register” on
page 13-424
08h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-425
0Ah
Section 13.2.6, “x_PIV—Prefetched Index Value
Register” on page 13-425
0Bh
Section 13.2.7, “x_CR—Control Register” on
page 13-426
10h
Section 13.2.1, “x_BDBAR—Buffer Descriptor Base
Address Register” on page 13-422
14h
Section 13.2.2, “x_CIV—Current Index Value
Register” on page 13-423
15h
Section 13.2.3, “x_LVI—Last Valid Index Register” on
page 13-423
16h
Section 13.2.4, “x_SR—Status Register” on
page 13-424
18h
Section 13.2.5, “x_PICB—Position In Current Buffer
Register” on page 13-425
Intel^® 82801CA ICH3-S Datasheet
511