82801CA Datasheet, PDF (3/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Intel^® 82801CA ICH3-S Features
s PCI Bus Interface
— Supports PCI Rev 2.2 Specification at 33 MHz
— 133 MByte/sec maximum throughput
— Supports up to 6 master devices on PCI
— One PCI REQ/GNT pair can be given higher
arbitration priority (intended for external
IEEE 1394 host controller)
s Integrated LAN Controller
— WfM 2.0 Compliant
— Interface to discrete Platform LAN Connect
component
— 10/100 Mbit/sec Ethernet support
s Integrated IDE Controller
— New: Supports "Native Mode" Register and
Interrupt support
— Independent timing of up to 4 drives, with separate
IDE connections for Primary and Secondary
cables
— Ultra ATA/100/66/33, BMIDE and PIO modes
s USB
— New: Includes 3 UHCI Host Controllers,
increasing the number of external ports to six
— Supports wake-up from sleeping states S1-S4
— Supports legacy Keyboard/Mouse software
s AC'97 Link for Audio and Telephony CODECs
— Audio Codec ’97, Revision 2.2 compliant
— Independent bus master logic for 5 channels (PCM
In/Out, Mic Input, Modem In/Out)
— Separate independent PCI functions for Audio and
Modem
— Support for up to six channels of PCM audio
output (full AC3 decode)
— Supports wake-up events
s Interrupt Controller
— Support up to 8 PCI interrupt pins
— Supports PCI 2.2 Message Signaled Interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports Serial Interrupt Protocol
— Supports Processor System Bus interrupt delivery
s 1.8 V operation with 3.3 V I/O
— 5V tolerant buffers on IDE, PCI, USB Over-
current and Legacy signals
s Timers Based on 82C54
— System timer, Refresh request, Speaker tone
output
s External Glue Integration
— Integrated Pull-up, Pull-down and Series
Termination resistors on IDE, processor interface,
and USB
s Power Management Logic
— ACPI 1.0 compliant
— ACPI-defined power states (C1–C2, S3–S5)
— ACPI Power Management Timer
— PME# support
— SMI# generation
— All registers readable/restorable for proper resume
from 0 V suspend states
— Support for APM-based legacy power
management for non-ACPI implementations
s Firmware Hub (FWH) Interface supports BIOS
Memory size up to 8 MB
s Low Pin count (LPC) Interface
— Allows connection of legacy ISA and X-Bus
devices such as Super I/O
— Supports two Master/DMA devices.
s Enhanced DMA Controller
— Two cascaded 8237 DMA controllers
— PCI DMA: Supports PC/PCI—Includes two
PC/PCI REQ#/GNT# pairs
— Supports LPC DMA
— Supports DMA Collection Buffer to provide
Type-F DMA performance for all DMA channels
s Real-Time Clock
— 256-byte battery-backed CMOS RAM
s System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon detection
of system hang
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— New: Supports ability to disable external devices
s SMBus
— Host interface allows processor to communicate
via SMBus
— Slave interface allows an external Microcontroller
to access system resources
— Compatible with most 2-Wire components that are
also I²C* compatible
— New: Supports SMBus 2.0 Specification
s GPIO
— TTL, Open-Drain, Inversion
s New: Package 31x31 mm 421 BGA
The Intel^® 82801CA ICH3-S may contain design defects or errors known as errata which may cause the products to deviate
from published specifications. Current characterized errata are available on request.
Intel^® 82801CA ICH3-S Datasheet
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