82801CA Datasheet, PDF (346/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

LPC I/F Bridge Registers (D31:F0)
9.8.3.11
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 30h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
32 bit
ACPI or Legacy
Bit
31:15
14
13
12
11
10:8
7
6
5
4
3
2
1
0
Description
Reserved.
PERIODIC_EN—R/W.
0 = Disable.
1 = Enables the ICH3 to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS
register.
TCO_EN—R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are
caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0,
NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
Reserved.
Microcontroller SMI Enable (MCSMI_EN)—R/W.
0 = Disable.
1 = Enables ICH3 to trap accesses to the microcontroller range (62h or 66h) and generate an
SMI#. Note that ’trapped’ cycles will be claimed by the ICH3 on PCI, but not forwarded to LPC.
Reserved.
BIOS Release (BIOS_RLS)—WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit
position by BIOS software.
Software SMI# Timer Enable (SWSMI_TMR_EN)—R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the
SMI# will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon
the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.
SWSMI_TMR_EN stays set until cleared by software.
APMC_EN—R/W.
0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN—R/W.
0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software
attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the
system will not transition to the sleep state based on that write to the SLP_EN bit.
LEGACY_USB_EN—R/W.
0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN—R/W.
0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit.
End of SMI (EOS)—R/W (special). This bit controls the arbitration of the SMI signal to the
processor. This bit must be set for the ICH3 to assert SMI# low to the processor.
0 = Once the ICH3 asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the
SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing
their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-
assert SMI upon detection of an SMI event and the setting of a SMI status bit.
GBL_SMI_EN—R/W.
0 = No SMI# will be generated by ICH3. This bit is reset by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
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Intel^® 82801CA ICH3-S Datasheet