82801CA Datasheet, PDF (411/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

SMBus Controller Registers (D31:F3)
12.2.15 NOTIFY_DADDR—Notify Device Address
Register Offset: 14h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DEVICE_ADDRESS—RO. This field contains the 7-bit device address received during the Host Notify
7:1 protocol of the SMBus 2.0 specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
0 Reserved.
12.2.16 NOTIFY_DLOW—Notify Data Low Byte Register
Register Offset: 16h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_LOW_BYTE—RO. This field contains the first (low) byte of data received during the Host Notify
7:0 protocol of the SMBus 2.0 specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
12.2.17 NOTIFY_DHIGH—Notify Data High Byte Register
Register Offset: 17h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_HIGH_BYTE—RO. This field contains the second (high) byte of data received during the Host
7:0 Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to 1.
Intel^® 82801CA ICH3-S Datasheet
411