82801CA Datasheet, PDF (131/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
Table 5-30. INIT# Going Active
Cause of INIT# Going Active
Comment
Shutdown special cycle from processor.
PORT92 write, where INIT_NOW (bit 0) transitions from a 0
to a 1.
PORTCF9 write, where RST_CPU (bit 2) was a 0 and
SYS_RST(bit 1) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected to be
driven by the external microcontroller (KBC).
0 to 1 transition on RCIN# must occur before
the ICH3 will arm INIT# to be generated again.
Note: RCIN# signal is expected to be high
during S1 and low during S3, S4, and S5
states. Transition on the RCIN# signal in
those states (or the transition to those
states) may not necessarily cause the
INIT# signal to be generated to the
processor.
CPU BIST
To enter BIST, the software sets CPU_BIST_EN
bit and then does a full processor reset using
the CF9 Register.
5.11.1.3 FERR#/IGNNE# (Coprocessor Error)
The ICH3 supports the coprocessor error function with the FERR#/IGNNE# pins. The function is
enabled via the COPROC_ERR_EN bit (Device 31:Function 0, Offset D0, bit 13). FERR# is tied
directly to the Coprocessor Error signal of the processor. If FERR# is driven active by the
processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR Register,
the ICH3 negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active until
FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.
Figure 5-12. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
If COPROC_ERR_EN is not set, then the assertion of FERR# will have not generate an internal
IRQ13, nor will the write to F0h generate IGNNE#.
Intel^® 82801CA ICH3-S Datasheet
131