82801CA Datasheet, PDF (426/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

AC ’97 Audio Controller Registers (D31:F5)
13.2.7
x_CR—Control Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 0Bh (PICR),
NABMBAR + 1Bh (POCR),
NABMBAR + 2Bh (MCCR)
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Bit
Description
7:5 Reserved.
Interrupt On Completion Enable (IOCE)—R/W. This bit controls whether or not an interrupt
occurs when a buffer completes with the IOC bit set in its descriptor.
4
0 = Disable. Interrupt will not occur.
1 = Enable.
FIFO Error Interrupt Enable (FEIE)—R/W. This bit controls whether the occurrence of a FIFO
error will cause an interrupt or not.
3
0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur.
1 = Enable. Interrupt will occur.
Last Valid Buffer Interrupt Enable (LVBIE)—R/W. This bit controls whether the completion of the
last valid buffer will cause an interrupt or not.
2
0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.
1 = Enable.
Reset Registers (RR)—R/W (special).
0 = Removes reset condition.
1
1 = Contents of all Bus master related registers to be reset, except the interrupt enable bits (bit
4,3,2 of this register). Software needs to set this bit but need not clear it since the bit is self
clearing. This bit must be set only when the Run/Pause bit is cleared. Setting it when the Run
bit is set will cause undefined consequences.
Run/Pause Bus Master (RPBM)—R/W.
0
0 = Pause bus master operation. This results in all state information being retained (i.e., master
mode operation can be stopped and then resumed).
1 = Run. Bus master operation starts.
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single 8-bit read
to offset 0Bh.
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Intel^® 82801CA ICH3-S Datasheet