82801CA Datasheet, PDF (133/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
When entering S1, the ICH3 asserts STPCLK# to both CPUs. In order to meet the processor
specifications, the CPUSLP# signal will have to be delayed until the 2^nd Stop-Grant cycle occurs.
To ensure this, the ICH3 will wait a minimum or 60 PCI clocks after receipt of the first Stop-Grant
cycle before asserting CPUSLP# (if the SLP_EN bit is set to 1).
Both processors must immediately respond to the STPCLK# assertion with stop grant
acknowledge cycles before the ICH3 asserts CPUSLP# in order to meet the processor setup time
for CPUSLP#. Meeting the processor setup time for CPUSLP# is not an issue if both processors are
idle when the system is entering S1. If it cannot be guaranteed that both processors will be idle, do
not enable the SLP_EN bit. Note that setting SLP_EN to 1 is not required to support S1 in a dual
processor configuration.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state, and thus
STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose
power. Upon exit from those states, the processors will have their power restored.
5.11.3 Speed Strapping for the Processor
The ICH3 directly sets the speed straps for the processor, saving the external logic that has been
needed with prior PCIsets. Refer to processor specification for speed strapping definition.
The ICH3 will perform the following to set the speed straps for the processor:
1. While PCIRST# is active, the ICH3 will drive A20M#, IGNNE#, NMI, and INTR high.
2. As soon as PWROK goes active, the ICH3 reads the FREQ_STRAP field contents.
3. The next step depends on the power state being exited as described in Table 5-33.
Table 5-33. Frequency Strap Behavior Based on Exit State
State
Exiting
ICH3
S1
There is no processor reset, so no frequency strap logic is used.
S3, S4, S5,
or G3
Based on PWROK going active, the ICH3 will deassert PCIRST#, and based on the value of the
FREQ_STRAP field (D31:F0,Offset D4), the ICH3 will drive the intended core frequency values
on A20M#, IGNNE#, NMI, and INTR. The ICH3 will hold these signals for 120 ns after
CPURST# is deasserted by the Host controller.
Table 5-34. Frequency Strap Bit Mapping
FREQ_STRAP Bits [3:0]
3
2
1
0
Sets High/Low Level for the Corresponding Signal
NMI
INTR
IGNNE#
A20M#
NOTE: The FREQ_STRAP Register is in the RTC well. The value in the register can be forced to 1111h via a
pinstrap (AC_SDOUT signal), or the ICH3 can automatically force the speed strapping to 1111h if the
processor fails to boot.
Intel^® 82801CA ICH3-S Datasheet
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