82801CA Datasheet, PDF (135/521 Pages) Intel Corporation – I/O Controller Hub 3-S (ICH3-S)

Functional Description
5.12.2 Intel^® ICH3 and System Power States
Table 5-35 shows the power states defined for ICH3-based platforms. The state names generally
match the corresponding ACPI states.
Table 5-35. General Power States for Systems using Intel^® ICH3
State/
Substates
Legacy Name / Description
G0/S0/C0
G0/S0/C1
Full On: processor operating. Individual devices may be shut down to save power. The
different processor operating levels are defined by Cx states, as shown in Table 5-36. Within
the C0 state, the ICH3 can throttle the STPCLK# signal to reduce power consumption. The
throttling can be initiated by software or by the THRM# input signal.
Auto-Halt: Processor has executed a AutoHalt instruction and is not executing code. The
processor snoops the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant t: The STPCLK# signal goes active to the processor. The processor performs a
Stop-Grant cycle, halts its instruction stream, and remains in that state until the STPCLK#
signal goes inactive. In the Stop-Grant state, the processor snoops the bus and maintains
cache coherency.
G1/S1
Stop-Grant: Similar to G0/S0/C2 state. ICH3 also has the option to assert the CPUSLP# signal
to further reduce processor power consumption.
Note: The behavior for this state is slightly different when supporting iA64 processors.
G1/S3
G1/S4
System to RAM (STR). The system context is maintained in system DRAM, but power is shut
off to non-critical circuits. Memory is maintained and refreshes continue. All clocks stop except
RTC clock.
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is
then shut off to the system except for the logic required to resume. Externally appears same as
S5, but may have different wake events.
G2/S5
G3
Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic
required to restart. A full boot is required when waking.
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the
RTC. No “Wake” events are possible, because the system does not have any power. This state
occurs if the user removes the batteries, turns off a mechanical switch, or if the system power
supply is at a level that is insufficient to power the “waking” logic. When system power returns,
transition depends on the state just prior to the entry to G3 and the AFTERG3 bit in the
GEN_PMCON3 Register (D31:F0, offset A4). Refer to Table 5-43 for more details.
Intel^® 82801CA ICH3-S Datasheet
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